Projects of the Design and diagnostics of digital systems department VEGA – Scientific Grant Agency of SR and SAS
ASFEU – Agency of SR for EU Structural Funds
SRDA – Agency for research&development support
MAD – Inter-academic agreement

Actual and recent projects:

Processing of sensor data via Artificial Intelligence methods.
Spracovanie údajov zo senzorov prostriedkami umelej inteligencie
Program: VEGA
Project leader: Ing. Malík Peter PhD.
ID: VEGA 2/0155/19
Duration: 1.1.2019 – 31.12.2022
Annotation

Finished projects:

Testable and Reconfigurable Digital Cores
Testovateľné a rekonfigurovateľné digitálne jadrá
Program: Inter-governmental agreement
Project leader: Doc. RNDr. Gramatová Elena CSc.
ID: 14
Duration: 1.1.2004 – 31.12.2007
Annotation
Design and Diagnostics of Electronic Circuits and Systems Workshop
Workshop o návrhu a diagnostike elektronických obvodov a systémov
Program: International Visegrad Found (IVF)
Project leader: Doc. RNDr. Gramatová Elena CSc.
ID: 12745
Duration: 1.2.2008 – 31.7.2008
Annotation
Techniques and Algorithms for Digital Systems on Chip Testing Optimisation
Metódy a algoritmy optimalizácie testovania digitálnych systémov na čipe
Program: VEGA
Project leader: Doc. RNDr. Gramatová Elena CSc.
ID: 2/5123/27
Duration: 1.1.2005 – 31.12.2007
Annotation
Mictoelectronics in secondary education network
Mikroelektronika v sieti stredoškolského vzdelávania
Program: SRDA
Project leader: Doc. RNDr. Gramatová Elena CSc.
ID: LPP-0021-06
Duration: 1.10.2006 – 30.9.2009
Annotation
New architectures for increasing the reliability of digital cores and systems
Nové architektúry na zvýšenie spoľahlivosti digitálnych jadier a systémov
Program: VEGA
Project leader: Ing. Baláž Marcel PhD.
ID: 2/0192/15
Duration: 1.1.2015 – 31.12.2018
Annotation
Reliable architectures and digital systems testability
Spoľahlivostné architektúry a testovateľnosť digitálnych systémov
Program: VEGA
Project leader: Doc. RNDr. Gramatová Elena CSc.
ID: 2/0135/08
Duration: 1.1.2008 – 31.12.2010
Annotation
Virtual digital design laboratory for high schools
Virtuálne laboratórium digitálneho návrhu pre stredné školy
Program: SRDA
Project leader: Ing. Malík Peter PhD.
ID: LPP-0149-09
Duration: 1.9.2009 – 31.8.2012
Annotation
Built-in self-repair for logic cores embedded in system-on-chip
Vstavaná samočinná opraviteľnosť logických jadier vnorených v systémoch na čipe
Program: VEGA
Project leader: Ing. Baláž Marcel PhD.
ID: 2/0034/12
Duration: 1.1.2012 – 31.12.2014
Annotation
(CRISIS)
Výskum a vývoj nových informačných technológií na predvídanie a riešenie krízových situácií a bezpečnosť obyvateľstva
Program: EU Structural Funds Research Development
Project leader: doc. Ing. Hluchý Ladislav CSc.
ID: ITMS 26240220060
Duration: 3.1.2011 – 31.12.2013

Actual and recent projects (annotations):

Processing of sensor data via Artificial Intelligence methods.
Spracovanie údajov zo senzorov prostriedkami umelej inteligencie
Annotation: The project will propose new methods and algorithms for processing of multi-sensor data for tasks of object diagnostics, areas of interest evaluation, secure communication and simplification of the new intelligent models creation. The research will focus on advanced methods of artificial intelligence with emphasis on deep learning. Artificial Intelligence algorithms show significantly better results than traditional methods, and an example of this is the tremendous progress of refining semantic image segmentation through deep learning over the last five years. Modern, low-cost, miniature electro-mechanical structures allow simple integration and group deployment of multiple sensors, resulting in the production of a huge amount of multi-sensor data that can not be manually processed. The project output will include new models of accurate semantic image segmentation, precision object modeling, multiple sensor collaboration models, and secure data transfer, especially for the Internet of Things and Industry 4.0.

Finished projects (annotations):

Testable and Reconfigurable Digital Cores
Testovateľné a rekonfigurovateľné digitálne jadrá
Annotation: The project is targeted to the self-testing techniques for digital systems and their applicability to logic circuits and memories. The project topics were solved in both institutions based on mobility of PhD students and young scientists during 3 project years.

Design and Diagnostics of Electronic Circuits and Systems Workshop
Workshop o návrhu a diagnostike elektronických obvodov a systémov
Annotation: The object of the project is organisation of the 11th international Workshop on Design and Diagnostics of Electronic Circuits and Systems that takes place annually in V4 countries. In April 2008 it will be organised in Bratislava. with the emphasis to enable a higher participation of prospective paper authors, mainly students, from universities, research institutions and industrial companies in V4 countries. The organiser is the Institute of Informatics of SAS in close cooperation with partners from Czech, Hungarian and Polish universities.

Techniques and Algorithms for Digital Systems on Chip Testing Optimisation
Metódy a algoritmy optimalizácie testovania digitálnych systémov na čipe
Annotation: The project topics are techniques and algorithms for optimum design of (self-) testability structures built-in and implemented on chip. The project indirectly follows up the object of the previous VEGA project (2/2066/22) in which testability of data encryption algorithms implemented into digital circuits have been solved. The achieved results have shown existence of variety techniques and their hardware solutions, standards for (self-) testability, but they haven not always to be applied by optimum and effective way. The optimization of existing and new developed methods is based on the achieved knowledge and experiences and is solved with respect to important parameters: test time, power consumption, overheads and cost needed for (self-) testing and fault diagnosis. The research object is a digital system implemented into FPGA or ASIC that consists of different digital blocks – cores (pre-designed or glue logic). The testing standards: IEEE 1500 SECT (the standard for embedded cores), IEEE 1149.1 Test Access Port and Boundary Architecture (JTAG), existing self-test techniques based on linear feedback shift registers (LFSR), cellular automata and data compaction and compression techniques are initial methods of the project. The expected contribution is in new algorithms and techniques, their optimum hardware and software implementation with regards to mentioned parameters and a system of their automatic synthesis to VHDL digital circuits and systems models.

Mictoelectronics in secondary education network
Mikroelektronika v sieti stredoškolského vzdelávania
Annotation: The project is focused on development of high-school network of mini-centres dealing with design of digital circuits, with methodical coordination by the Slovak academy of sciences research team. The pilot mini-centres, established at four selected high-schools, will have licences of professional computer aided design tools for integrated circuits FPGA (field programmable gate array). By help of easy-to-understand hands-on teaching materials, examples for beginners and advanced, self-work tasks with help of trained teachers and research team, the students will learn about digital design fundamentals in current technologies. The knowledge and skill obtained will enhance the interest of young people in microelectronics and in the use of new technologies in research and practice. In the end of the project, the experience gained by the teachers and researchers, as well as the results of the students´ work in the mini-centres will be provided to other high-schools and presented to public. The verified teaching materials and procedures will be processed as methodical manual.

New architectures for increasing the reliability of digital cores and systems
Nové architektúry na zvýšenie spoľahlivosti digitálnych jadier a systémov
Annotation: Complex systems integrated on a chip are becoming ubiquitous in many applications; so their operation must be reliable and resistant to failure, even though the nanotechnologies enhance their failure rate as a result of newfault mechanisms. Reliability of systems-on-chip (SoCs) is becoming a critical parameter and often could be achieved only at the expense of other parameters quality, such as consumption and chip area. The project aims to research on new architectures with built-in self-repair suited to different types of digital IP cores embedded inSoCs. In addition to standard cores such as processors, controllers, and other combinational cores, the project focuses on the so-called specialized cores, for which there are currently no methods to increase their reliability.The proposed architecture will be verified by simulation through the available software tools and experimentally using programmable devices. The results of the project will contribute to increasing reliability and life-cycle of SoCs.

Reliable architectures and digital systems testability
Spoľahlivostné architektúry a testovateľnosť digitálnych systémov
Annotation: The aim of the project is design and implementation of new reliably solved architectures for digital systems fault diagnosis and fault self-repairing. Testing of complex digital systems on chip requires more and more hardware blocks, such as self-test generators, compression and decompression units, signature analysers, standard interfaces for embedded core inputs and outputs accessibility, and different types of control units. Increasing test hardware overhead, a new problem arises, namely its reliability. Project results will help to improve the quality of testability, reliability and operating life of digital systems by introducing new strategies and procedures, which will connect methods of concurrent and off-line diagnostics in systems, as well as in blocks determined for those systems testing. Proposed new methods will be verified by their applications to real digital systems using the FPGA technology. The selection will be targeted at systems for data encryption algorithms, image and audio processing.

Virtual digital design laboratory for high schools
Virtuálne laboratórium digitálneho návrhu pre stredné školy
Annotation: The project goal is to create a virtual laboratory for the digital circuits design for students of electrical engineering and applied informatics secondary schools. The project follow up results on the project MikroN (LPP-0021-06). The virtual laboratory will provide access to proffesional design software FPGA, new special interactive education tools and design of digital systems textbooks. The project will also provide courses of design software usage with methodical handbooks for teachers and students, new thesis required for the school leaving examination, competitions and expert practice of students in the research institution, and special lessons from selected topics of electrical engineering, electrical technology and computer systems presented by researcher of the II SAS at secondary schools. The virtual laboratory will be distributed at seven workplaces and will use a new electronic portal developed as the result of mutual cooperation.

Built-in self-repair for logic cores embedded in system-on-chip
Vstavaná samočinná opraviteľnosť logických jadier vnorených v systémoch na čipe
Annotation: Maintaining the reliability of the digital system during its lifetime becomes the most important challenge for the current semiconductor industry. It is required to design highly reliable systems even if the system components reliability shows the decreasing tendency due to new fault mechanisms in the modern nanotechnologies. Reliability of complex systems integrated on a single chip is not possible without the implementation of self-repair capability. Application of such architectures is well known for memory circuits and other regular structures. The goal of the proposed project is the development of new methods for designing built-in self-repair architectures for circuits with irregular structures (combinational and sequential logic circuits). The developed methods will be evaluated on selected types of logic cores by simulation using available software tools and programmable circuits. The results of the proposed project contribute to the reliability increase of the systems-on-chip.