Oddelenie návrhu a diagnostiky číslicových systémov
Institute of Informatics
 

Zoznam vybratých publikácií

2008
  1. Gramatová, E., Fischerová, M.: Memory test, BIST and self repair. In Design and Test Technology for Dependable Hardware/Software Systems. - Cottbus : BTU, 2008, 2008, cD, 84 slides.
  2. Mánik, M., Gramatová, E.: Boolean formalisation of the PMC model for faulty units diagnosis in regular multi-processor systems. In 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems : proceedings. - Bratislava : The Institute of Electrical and Electronic Engineers, 2008. ISBN 978-1-4244-2276-0, p. 144-145.
  3. Malík, P., Baláž, M., Šimlaštík, M., Luczyk, A., Pleskacz, W.: Various MDCT implementations in 0.34um CMOS. In 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems : proceedings. - Bratislava : The Institute of Electrical and Electronic Engineers, 2008. ISBN 978-1-4244-2276-0, p. 170-173.
  4. Dobai, R.: Design for delay testability of asynchronous digital circuits. In Počítačové architektury a diagnostika 2008. Editor Zdeněk Plíva, Martin Rozkovec. - Liberec : Technická univerzita, 2008. ISBN 978-80-7372-378-1, p. 11-16.
2007
  1. Malík, P.,Baláž, M.,Pikula, T.,Šimlaštík, M.: An improved MDCT IP core generator with architectural model simulation. In 2007 IEEE Workshop on design and diagnostics of electronic circuits and systems : proceedings. - IEEE. ISBN 1-4244-1161-0, s. 193-198.
  2. Šimlaštík, M., Stopiaková,V., Majer, L., Malík, P.: Clockless implementation of LEON2 for low-power applications. In 2007 IEEE Workshop on design and diagnostics of electronic circuits and systems : proceedings. - IEEE. ISBN 1-4244-1161-0, s. 215-218.
  3. Malík, P.: A genetic IP Core of Indetical Forward and Inverse 12/36 Point MDCT Architecture and an Architectural model Simulation Toolbox. 14th IEEE International Conference on Electronics, Cirsuits and Systems, December 11-14, 2007, Marrakech, Maroko.
  4. Gramatová, E., Fischerová, M., Smiščík, R.: Software tool for on-line testing techniques application. In ECP´07 : proceedings of the 6th Electronic Circuits and Systems Conference. - Bratislava : Vydavatežstvo STU, 2007. ISBN 978-80-227-2697-9, p. 133-136.
  5. Mánik, M.: An extended Boolean method in the PMC system model for faulty units identification. In ECS´07 : proceedings of the 6th Electronic Circuits and Systems Conference. - Bratislava : STU Bratislava, 2007. ISBN 978-80-227-2697-9, p. 155-158.
2006
  1. Šimlaštík, M., Malík, P., Pikula, T., Baláž, M.: FPGA implementation of a fast MDCT algorithm. In NOVÁK, Ondřej. 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems : proceedings. Praha : Czech Technical University Publishing House. ISBN 1-4244-0184-4. S. 228-229.
  2. A. Bosio, S. di Carlo, G. di Natale, M. Fischerová, T. Pikula, M. Šimlaštík: Interactive Educatinoal Tool for Memory Testing, Proc. of the 6th European Workshop on Microelectronics Education (EWME 2006), Stockholm, Sweden, June 8-9, 2006, ISBN 91-7178-402-0, s.
  3. Baláž, M., Malík, P., Pikula, T., Šimlaštík, M.: MDCT IP Core Generator, Proc. of IEEE 1st International Conference on Design and Test of Integrated Systems in Nanoscale Technology (IEEE DTIS 2006), Tunis, Tunisia, September 5-7, 2006, IEEE Catalog number 06EX1441C, ISBN 0-7803-97274-4, s. 327-330.
  4. Gramatová, E.: Test Generation Experiments for Delay Fault in Digital Circuits, Proc. of Electronic Devices and Systems Conference (EDS 2006), Brno, Česká republika, september 2006, ISBN 80-214-3246-2, s. 74-78.
  5. Fischerová, M., T. Pikula, T., Šimlaštík, M., Bosio, A., S. di Carlo, G. di Natale: A tool for teaching memory testing based on BIST, Proc. of IEEE International Baltic Electronics Conference (BEC 2006), Tallinn, Estonia, October 2-4, 2006, IEEE Catalog number 06EX1695, ISBN 1-4244-0414-2, s. 187-190.
  6. Malík, P., Baláž, M., Pikula, T., Šimlaštík, M.: MDCT IP Core Generator with Architectural Model Simulation, Proc. of IFIP International Conference on Very Large -Scale Integration (VLSI-SoC2006), Nice, France, October 16-18, 2006, IEEE Catalog number 06EX1450, ISBN 3-901882-19-7, s. 18-23.
2005
  1. Baláž, M., Pikula, T., Trebatický, P., Ladecký, V., Ševčík, R.: Testovatelné jadrá pre šifrovanie algoritmom Rijndael. Acta Electronica et Informatica (casopis), No.2, Vol.5, 2005, ISSN 1335-8243. Košice, Slovenská Republika, pp. 60-65.
  2. Malík, P., Trebatický, P., Ďuračková, D.: Návrh a implementácia rozhrania USB pre obvod šifrovania údajov. Proceedings of the 8th Internacional Conference Informatics 2005, ISBN 80-969243-3-8, Bratislava, Slovak Republic, jun 2005, pp. 100-112.
  3. Baláž, M., Fischerová, M., Gramatová, E., Jutman, A., Kotásek, Z., Novák, O., Pikula, T., Raik, J., Strnadel, J., Ubar, R., Záhradka, J.: Testing Tools forTtrainning and Education. Proceeding of the 12th International Conference MIXDES 2005, ISBN 83-919289-9-3, Krakow, Poland, june 2005, pp. 671-676.
  4. Malík, P., Trebatický, P., Ďuračková, D.: USB Comunication Interface for the Rijandel Data Encryption Algorithm. . Proceeding of the 12th International Conference MIXDES 2005, ISBN 83-919289-9-3, Krakow, Poland, june 2005, pp. 219-221.
  5. Fischerová, M., Šimlaštík, M.: MemBIST Applet for Learning Principles of Memory Testing and Generation Memory BIST. Proceedings of the IEEE 8th Euromicro Conference on Digital System Design (DSD 2005), Porto, Portugal, august 2005, pp. 276-281.
  6. Pikula, T., Giorgio di Natale, Gramatová, E.: Built-in Self-Test Generation for Delay Faults - A case study. Prceedings of the 5th Electronic Circuits and Systems Conference (ECS'05), Bratislava, Slovak Republic, september 2005, pp. 11- 14.
  7. Malík, P., Trebatický, P., Ďuračková, D.: FPGA Impementation of the USB Communication Interface for the Rijandel Data Encryption Algorithm. Prceedings of the 5th Electronic Circuits and Systems Conference (ECS'05), Bratislava, Slovak Republic, september 2005, pp. 123- 126.
  8. Baláž, M. : Architektúra Testovacieho Okolia Jadra s Dekóderom Testov (PAD'05). Zborník z česko- slovenského seminára pre študentov doktorandského štúdia, Lázně Sedmihorky, Česká Republika, september 2005, pp. 7-12.
  9. Pikula, T.: Vstavané Generátory Testov Pre Poruchy Oneskorení (PAD'05). Zborník z česko- slovenského seminára pre študentov doktorandského štúdia, Lázně Sedmihorky, Ceska Republika, september 2005, pp. 141- 1
  10. Baláž, M., Gramatová, E., Pikula, T., Fischerová;, M.: eTool for Teaching and Application of Digital System Testability Techniques. In EUROCON 2005, Belegrade, Serbia and Monte Negro, november 2005, pp. 831-834.
  11. Novák, O., Gramatová, E., Ubar, R.: Handbook of Testing Electronic Systems. Vydavatel: CVUT Praha, 2005
  12. Baláž, M., Pikula,T.: Handbook of Testing Electronic Systems. Appendix1. Testing Tools. Vydavatel: CVUT Praha, 2005, pp.3.
  13. Fischerová;, M.: Handbook of Testing Electronic Systems. Príspevky do kapitol Defects, Faults, Fault Models, Test Generation Techniques and Algorithms, Appendix1.Testing Tools. Vydavatel: CVUT Praha, 2005, pp. 25.
  14. Gramatová, E.: Handbook of Testing Electronic Systems. Príspevky do kapitol Defects, Faults, Fault Models, Test Generation Techniques and Algorithms, Appendix1.Testing Tools. Vydavatel: CVUT Praha, 2005, pp. 35.
2004
  1. Ladecký, V., Ševčík, R., Baláž, M.: FPGA Implementation of the Rijndael Algorithm for Data Encryption.In: Proceedings of the IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Stará Lesná, Slovakia, April 2004, ISBN 80-969117-9-1, pp. 265-267.
  2. Ševčík, R., Pikula, T.: STUMPS Architecture Generation by a Java Applet. In: Proceedings of the IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Stará Lesná, Slovakia, April 2004, ISBN 80-969117-9-1, pp. 271-273.
  3. Baláž, M., Gramatová, E.: Wrapper Connection Technique for Embedded Cores. Proceedings of the 9th Biennial Baltic Electronics Conference (BEC), ISBN 9985-59-462-2, Tallinn, Estonia, október 2004, pp. 209-212, (1,0).
  4. Mánik, M., Gramatová, E.: An Extended Formalisation in the PMC System Model for Faulty Units Identification. Proceedings of the 9th Biennial Baltic Electronics Conference (BEC), ISBN 9985-59-462-2,Tallinn, Estonia, október 2004, pp. 213-216, (0,5).
  5. Pikula, T., Lauko, R.: BIST Learning Applet. Proceedings of the 9th Biennial Baltic Electronics Conference (BEC), ISBN 9985-59-462-2, Tallinn, Estonia, október 2004, pp. 259-2262, (0,5).
  6. Pikula, T.: Vstavané samočinné testovanie SOC. Zborník z česko-slovenského seminára pre študentov doktorandského štúdia PAD 2004, ISBN 80-969202-0-0, Moravany nad Váhom, Slovensko, september 2004, pp. 84-87, (1,0).
  7. Baláž, M.: Prístupové testovacie architektúry pre digitálne systémy integrované na čipe. Zborník z česko- slovenského seminára pre študentov doktorandského štúdia PAD 2004, ISBN 80-969202-0-0, Moravany nad Váhom, Slovensko, september 2004, pp. 72-77, (1,0).
  8. Gramatová, E., Fischerová, M., Pikula, T., Baláž, M., Lauko, R., Trebatický, P.: Training Set for Design Testability and Built-in Self-test Techniques of Digital Circuits and Systems. Proceedings of the49. Internationales Wissenschaftliches Kolloquium, Ilmenau, Shaker VERLAG, ISBN 3-8322-2824 september 2004, pp. 498-504, (0,9).
  9. Jutman, A., Gramatová, E., Pikula, T., Ubar, R.: E-learning Tools for Teaching Self-Test of Digital Electronics. Proceedings of 15th EAEEIE Conference on Innovation in Education for Electrical and Information Engineering, Sofia, Bulgaria, máj 2004, pp. 267-272, (0,5).
  10. Baláž, M., Pikula, T., Lauko, R., Fischerová, M., Gramatová, E.: eLearning and eTraining Tools for Testability Techniques of Digital Circuits and Systems. Proceedings of the 5th International Conference Virtual University, Bratislava, Slovak Republic, december 2004, pp. 95-100, (0,8).
  11. Gramatová, E., Fischerová, M.: Zborník z česko- slovenského seminára pre študentov doktorandského štúdia PAD 2004. ISBN 80-969202-0-0, Moravany nad Váhom, Slovensko, september 2004, editori zborníka.
2003
  1. Baláž, M., Gramatová, E., Fischerová, M.: Test Wrapper Application To Embedded Cores as a Java Applet. In: Proceedings of the IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Poznañ, Poland, April 2003, ISBN 83-7143-557-6, pp. 33-40.
  2. Pikula, T., Gramatová, E.: BIST Architecture Application for Digital Circuits as a Java Applet. In: Proceedings of the IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Poznañ, Poland, April 2003, ISBN 83-7143-557-6, pp. 305-306.
  3. Baláž, M., Gramatová, E.: Optimization Techniques for Parallel Interface of Test Wrapper for Embedded Cores. In: Digest of papers, IEEE European Test Workshop (ETW), Maastricht, The Netherlands, May 2003, pp. 25-26.
  4. Pikula, T., Gramatová, E., Fischerová, M.: Automatic Design of Cellular Automata for Generating Deterministic Test Patterns. In: Digest of Papers, IEEE European Test Workshop (ETW), Maastricht, The Netherlands, May 2003, pp. 285-286.
  5. Baláž, M., Pikula, T., Trebatický, P.: FPGA-based Implementation of a Data Encryption Algorithm with Testability Structures. In: Proceedings of the 4th Electronic Circuits and Systems Conference (ECS), ISBN 80-227-1939-0, Bratislava, Slovakia, September, 2003, pp. 155-158.
  6. Baláž, M., Gramatová, E., Fischerová, M.: Automatic Optimization of Wrapper Parallel Interface Constructions Applied to Digital Cores. In: Proceedings of the IEEE Region 8 EUROCON 2003 Conference, Ljubljana, Slovenia, September 2003, pp. 44-47.
  7. Pikula, T., Gramatová, E., Fischerová, M.: Deterministic Test Generation for Digital Circuits by Cellular Automata in a Java Applet.In: Proceedings of the IEEE Region 8 EUROCON 2003 Conference, Ljubljana, Slovenia, September 2003, pp . 40-43.
2002
  1. Cibáková, T., Fischerová, M., Gramatová, E., Kuzmicz, W., Pleskacz, W.A., Raik, J., Ubar, R.: Hierarchical test generation for combinational circuits with real defect coverage. In : Microelectronics Reliability 42 (2002), pp. 1141-1149.
  2. Schneider, A., Ivask, E., Mikloš, P., Raik, J., Diener, K.H., Ubar, R., Cibáková, T., Gramatová, E.: Internet-based Collaborative Test Generation with MOSCITO. In : Proceedings 2002 Design, Automation and Test in Europe (DATE), Paris, France, March, 2002, pp. 221-226.
  3. Baláž, M., Pikula, T., Trebatický, P., Gramatová E.: Memory Self-Testing Using a Non-Linear Cellular Automaton in the Circuit for Data Encryption. In: Proceedings of the IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), ISBN 80-214-2094-4, Brno, Czech Republic, April 2002, pp. 352-355.
  4. Baláž, M., Gramatová, E., Fischerová, M.: Automatic Synthesis of Testing Ports for Digital Circuits. In: Proceedings of the eleventh International Electrotechnical and Computer Science Conference ERK 2002, Portorož, Slovenia, ISSN 1581-4572, September, 2002, pp. 65-68.
  5. Schneider, K., Diener, H., Gramatová, E., Fischerová, M., Ivask, E., Ubar, R., Pleskacz, W., Kuzmicz, W.: Defect-Oriented Test Generation and Fault Simulation in the Enviroment of MOSCITO. In: Proceedings of the 8th Biennial Baltic Electronics Conference (BEC), ISBN 9985-59-292-1 Tallinn, Estonia, October 2002, pp. 303-305.
  6. Pikula, T., Fischerová, M., Gramatová, E.: Automatic Synthesis BIST Tool for Digital Circuits In: Proceedings of the 8th Biennial Baltic Electronics Conference (BEC), ISBN 9985-59-292-1, Tallinn, Estonia, October 2002, pp. 261-263.
2001
  1. J. Štefanovič, P. Mikloš, E. Gramatová: A New Open Platform for VHDL Modelling at the Behavioural Level, Proc. of the 4th DDECS 2001, Gyor, Hungary, April 2001, pp. 141-144.
  2. T. Cibáková, E. Gramatová, W. Kuzmicz, W. Pleskacz, J. Raik, R. Ubar: Defect-Oriented Library Builder and Hierarchical Test Generation, Proc. of the 4th DDECS 2001, Gyor, Hungary, April 2001, pp. 163-168.
  3. J. Štefanovič, P. Mikloš, E. Gramatová, M. Fischerová: Test Pattern Generation Using a New Open Platform at the Behavioural Level, Informal Digest of the IEEE European Test Workshop, Stockholm, Sweden, May 2001, pp. 211-213.
  4. T. Cibáková, M. Fischerová, E. Gramatová, W. Kuzmicz, W. Pleskacz, J. Raik, R. Ubar: Defect-Oriented Test Generation Using Probabilistic Estimation, Proc. of the 8th International Conference MIXDES, Zakopane, Poland, June 2001, pp. 131-136.
  5. T. Cibáková, E. Gramatová, W. Kuzmicz, P. Mikloš, W. Pleskacz: Defect-Oriented Test Pattern Generation for Circuits with Complex Gates, Proc. the of 3rd ECS Conference, Bratislava, Slovakia, September 2001, pp. 3-6.
  6. J. Štefanovič, P. Mikloš, E. Gramatová, M. Fischerová: Test Pattern Generation Using a New Open Platform at the Behavioural Level, Proc. of the 3rd ECS Conference, Bratislava, Slovakia, September 2001, pp. 7-10.
2000
  1. E. Gramatová, J. Gašpar, T. Cibáková: Fault Simulation for Combined and Voltage Testing of Combinational Circuits, Proc. of the 3rd DDECS Workshop, Smolenice, Slovakia, April 2000, pp. 52-58.
  2. M. Blyzniuk, T. Cibáková, E. Gramatová, W. Kuzmicz, M. Lobur, W. Pleskacz, J. Raik, R. Ubar: Hierarchical Defect-Oriented Fault Simulation for Digital Circuits, Informal Digest of the IEEE European Test Workshop 2000, Cascais, Portugal, May 2000, pp. 151-156.
  3. M. Blyzniuk, T. Cibáková, E. Gramatová, W. Kuzmicz, M. Lobur, W. Pleskacz, J. Raik, R. Ubar: Hierarchical Defect-Oriented Fault Simulation for Digital Circuits, Proc. of the IEEE European Test Workshop 2000, Cascais, Portugal, May 2000, pp. 69-74.
  4. M. Blyzniuk, T. Cibáková, E. Gramatová, W. Kuzmicz, M. Lobur, W. Pleskacz, J. Raik, R. Ubar: Defect-Oriented Fault Coverage of 100% Stuck-at Fault Test Sets, Proc. of the 7th International Conference MIXDES, Szcyrk, Poland, June 2000, pp. 511-516.
  5. E. Gramatová, T. Cibáková, J. Gašpar, P. Mikloš: ATPG for IDDQ and/or Voltage Testing of Combinational Circuits Using an Arbitrary Fault Library for Basic Gates, Informal Digest of the IEEE European Test Workshop, Cascais, Portugal, May 2000, pp. 317-318.
  6. J. Štefanovič: Automatic Generation Algorithm for Behavioral Benchmark Circuits, Proc. of the 3rd DDECS 2000, Smolenice, Slovakia, ISBN 80-968320-3-4 Polygrafia SAV Slovakia, pp. 67-70.
  7. M. Blyzniuk, T. Cibáková, E. Gramatová, W. Kuzmicz, M. Lobur, W. Pleskacz, J. Raik, R. Ubar: Hierarchical Defect-Oriented Fault Simulation for Digital Circuits, 2nd VILAB USER FORUM, Smolenice, Slovakia, April 2000.
  8. V. Vorisek: Built-in Test Pattern Generators for Logic BIST Structures in Digital Circuits and Systems, state of the art to the PhD exam, March 2000 (in Slovak)
  9. P. Mikloš: Compiler from VHDL/RTL languages into Simulation Form. Diploma theses 1999/2000, FEI STU Bratislava (in Slovak).
  10. E. Gramatová: Activities of Slovak Research Institutes and Universities in New Technologies Transfer, Compendium of the 3rd VILAB USER FORUM, Tallinn, Estonia, October 2000.
1999
  1. E. Gramatová, J. Bečková, J. Gašpar: defect Oriented TPG for Combinational IDDQ - Voltage Testing for Combinational Circuits, Proc. of EDCC-3, Praha, Czech republik, 1999, pp. 5-6.
  2. E. Gramatová, J. Bečková, J. Gašpar: TPG for Combinard Iddq-Voltage Testing of Combinational Circuits, Proc. of 2nd ECS Conference, Bratislava, Slovakia, September 1999, pp. 29-32.
1998
  1. E.Gramatová, A.Somorovská, J.Gašpar, H.Manhaeve: Random and Deterministic Test Pattern Generation for IDDQ-Voltage Testing, Proc. of 5th Electronic Devices and Systems Conference, Brno, 1998, pp.205-208.
  2. E. Gramatová, A.Somorovská, J.Gašpar, H.Manhaeve: Test Pattern Generation System for IDDQ-Voltage Test Experiments, Proc. of ETW'98, Sitges, Spain, pp. 193-194.
1997
  1. E. Gramatová, J. Bezáková, M. Fischerová: BX-TPG Algorithm at the Behavioural Level Implemented under LEDA VHDL System, Proc. of European Test Workshop, Cagliari, Italy, 1997, 2 p, poster.
  2. P.Gramata, E.Gramatová, A.Somorovská, H. Manhaeve: Built-In Implementation of Pre-Computed Deterministic Test Set for IDDQ/Voltage Testing, Proc. of the 1st Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 1997, pp. 181-184.
  3. J. Štefanovič, E.Gramatová: VLSI Functional Test Generation and Genetic Algorithms, Proc. of Artificial Intelligence and Information - Control Systems of Robots, Smolenice, Slovakia, 1997, pp. 347-355.
1996
  1. E. Gramatová, M. Fischerová: Delay Fault Investigation at the Higher-Level, Proc. of abstracts, of the 3rd BELSIGN Workshop, 1996, 2 p.
  2. M. Fischerová, E. Gramatová: Delay Fault Investigation at the Register Transfer Level, Proc. of the Baltic Electronic Conference, Tallinn, Estonia, 1996, pp. 141-144.
  3. E. Gramatová, J. Bezáková, T. Cibáková: Test Pattern Generation at the Behavioural Level from VHDL Circuit Description Containing Several Processes, Proc. of the Baltic Electronic Conference, Tallinn, Estonia, 1996, pp. 145-148.
  4. K. Kosuk, P. Gramata: BIST Structures for Digital Circuits for IDDQ Testing, Proc. of the UBISTA/FUTEG Workshop, Dresden, Germany, 1996, 7 p.
  5. E. Gramatová, J. Bezáková, M. Fischerová: TPG algorithm at the Behavioural Level (BX-Algorithm), Proc. of the UBISTA/FUTEG Workshop, Dresden, Germany, 1996, 9 p.
  6. E. Gramatová, A. Somorovská: TPG Algorithm for IDDQ Testing Based on Critical Path Tracing, Proc. of the UBISTA/FUTEG/Workshop, Dresden, Germany, 1996, 13 p.
1995
  1. E. Gramatová, T. Cibáková: Test Pattern Generation Algorithm on the Behavioral Level, 2nd FUTEG Workshop, Kaunas, Lithuania, 1995, 9 p.
  2. M. Duda, J. Bezáková, E. Gramatová: Fault Simulation Algorithm at the Behavioral Level, 2nd FUTEG Workshop, Kaunas, Lithuania, 1995, 10 p.
  3. J. Štefanovič, E. Gramatová: RTL Level Test Generation Using Genetic Algorithm and Simulated Annealing, Proc. of the 2nd Workshop on Hierarchical Test Generation, Duisburg, Germany, 1995, pp. 30.
  4. M. Duda, J. Bezáková, E. Gramatová: Fault Simulation on Behavioral Level from VHDL Circuit Description Containing Several Processes, Proc. of the 2nd Workshop on Hierarchical Test Generation, Duisburg, Germany, 1995, pp. 39.
  5. E. Gramatová, T. Cibáková: Test Generation Algorithms for Digital Structures at the Behavioral Level, Proc. of Seminar Design and Diagnostics of Electronic Circuits and Systems '95, Roznov pod Radhostem, Czech Republic, 1995, pp. 29-38.
  6. J. Štefanovič, E. Gramatová: Genetic Algorithms in the Test Pattern Generation for Digital Structures, Proc. of Seminar Design and Diagnostics of Electronic Circuits and Systems '95, Roznov pod Radhostem, Czech Republic, 1995, pp. 44-47.
  7. J. Štefanovič, E. Gramatová: Genetic Algorithms in the Test Generation on Register-Transfer Level, Proc. of Design Methodologies for Microelectronics, Smolenice, Slovakia, 1995, pp. 217-218.
1994
  1. M. Duda: Comparison of Fault Model on RT-level and Behavioral Level, Proc. of 1st EEMCN Workshop, Bratislava, Slovakia, 1994, 5p.
  2. E. Gramatová: Research Activities in the TPG and Fault Simulation Algorithms at the Institute of Computer Systems, Proc. of 1st EEMCN Workshop, Bratislava, Slovakia, 1994.
  3. P. Gramata, P. Trebatický, E. Gramatová: The MD5 Message-Digest Algorithm in the XILINX FPGA, poster, Proc. of Field-Programmable Logic, Prague, Czech Republic, 1994, pp. 126-128.
1993
  1. A. Magdolen, J. Bezáková, E. Gramatová, M. Fischerová: REGGEN - Test Pattern Generation on Register Transfer Level, Proc. of EURO-DAC'93 with EURO-VHDL'93, Hamburg, Germany, 1993, pp. 259-264.
  2. P. Gramata: Possibilities to Use FPGA for Encryption of Binary Information, Proc. of User Forum and EUROASIC Prizes, EUROASIC'93 and EDAC'93, Paris, France, pp. 248-251.
1992
  1. J. Štefanovič: Simulation of Digital Circuits on the Register Transfer Level, Computer and Artificial Intelligence, Vol. 11., No. 6, 1992, pp. 585-596.
  2. A. Magdolen, J. Bezáková, E. Gramatová: Automatic Test Pattern Generation on Register Transfer Level, 1st Int. Workshop on System Test and Diagnosis, Freiburg, Germany, 1992, poster.
1990
  1. E. Gramatová: Functional Test Pattern Generation Techniques for Complex Digital Circuits, Proc. of Diagnostics of Microprocessor, Prague, Czech Republic, 1990, pp.35-43.
1989
  1. E. Gramatová: Test Pattern Generation for VLSI Circuits, Proc. of Diagnosis, Reliability and Alarm Management in Continuos and Discrete Systems, Budapest, Hungary, 1989, pp.209-221.