Tutorial I – Defect-oriented Testing
April 18, 2004, 9:00 – 13:00

Michel Renovell
Realistic Fault Models for Spot Defects (45 min)

Given that eliminating all potential defects in today’s IC manufacturing technology is impossible, each manufactured IC must be tested such that defective parts not be shipped to customers. Typically, different IC test strategies are used since none alone is sufficient to achieve targeted low defect levels. Most IC manufacturers use one or more of the following three strategies: static voltage strategy or Boolean test; the dynamic voltage strategy or Delay test; and the static current strategy or IDDQ test. For test pattern generation or fault simulation purposes, each test strategy uses specific fault models. Of course the final objective is to detect defects not faults. Hence, the efficiency of the generated test sequence depends on a fault model’s ability to represent such defects behavior and location. It is clear that defects not correctly captured by the respective fault models can be partially responsible for higher resulting defect levels. Defect level reduction in ICs thus depends highly on improving fault model effectiveness in capturing defects. Many different spot defects are very likely to happen in today IC technologies. These spot defects are classically shorts and opens located in the interconnect or on the transistors themselves. In this presentation, the example of interconnect short is used to analyze in details the Boolean behavior of the defect and to define realistic model for this type of spot defect. The results are extended to other types of test strategy (Iddq, delay) and to other type of defect (floating gate, gate-oxide short..). The impact on Fault Simulation and ATPG is discussed.

Bibliography:
1. I.Polian, P.Engelke, M.Renovell, B.Becker. Modeling feedback bridging faults with non-zero resistance. Proc. of the 8th IEEE European Test Workshop ETW 2003, 25-28 May 2003, pp. 91 –96.
2. P.Girard, O.Heron, S.Pravossoudovitch, M.Renovell. Defect Analysis for Delay-Fault BIST in FPGs. Proc. of the 9th IEEE On-Line Testing Symposium – IOLTS 2003, 7-9 July 2003, pp. 124 –128.
3. M.Renovell, J.M.Galliere, F.Azais, Y.Bertrand. Modeling gate oxide short defects in CMOS minimum transistors. Proc. of the 8th IEEE European Test Workshop ETW 2003, 25-28 May 2003, pp. 15 –20.
4. M.Renovell, F.Azais, Y.Bertrand. Improving defect detection in static-voltage testing. Design & Test of Computers, IEEE , Volume: 19, Issue: 6, Nov.-Dec. 2002, pp.83 –89.

Witold A. Pleskacz
Defect Analysis and Probability Evaluation for Test Improvement (45 min)

In this tutorial lecture, a methodology for probabilistic modeling of physical defects in CMOS gates and estimation of the effectiveness of test patterns for detecting physical defects will be discussed. Quality of testing depends also on quality of test patterns generated for a circuit under test. Evaluation criteria for digital circuits testing are fault coverage and test application time. Low efficiency of the classical stuck-at fault model in real defect coverage in CMOS logic has initiated the need of new test approaches. These approaches extend the CMOS standard cells characterization methodology for voltage defect based testing and for IDDQ testing. The proposed methodology allows to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. For shorts at the inputs two types of cell simulation conditions – “Wired-AND” and “Wired-OR” – are used. Examples of industrial standard cells characterization indicate that a single logic fault probability table is not sufficient. Separate tables for “Wired-AND” and “Wired-OR” conditions at the inputs are needed for full characterization and hierarchical test generation.

Bibliography:
1. D.Kasprowicz, W.A.Pleskacz. Improvement of Integrated Circuit Testing Reliability by Using the Defect Based Approach. J. of Microelectronics Reliability, vol.43/6, June 2003, pp. 945-953.
2. W.A.Pleskacz, T.Borejko, W.Kuzmicz. CMOS Standard Cells Characterization for IDDQ Testing. Proc. of Defect and Fault Tolerance in VLSI Systems, Vancouver, Canada, Nov. 2002, pp. 390-398.
3. W.A.Pleskacz, D.Kasprowicz, T.Oleszczak, W.Kuzmicz. CMOS Standard Cells Characterization for Defect Based Testing. Proc. of Defect and Fault Tolerance in VLSI Systems, San Francisco, USA, Oct. 2001, pp. 384-392.
4. M.Blyzniuk, I.Kazymyra, W.Kuzmicz, W.A.Pleskacz, J.Raik, R.Ubar.
Probabilistic Analysis of CMOS Physical Defects in VLSI Circuits for Test Coverage Improvements. Journal of Microelectronics Reliability. Pergamon Press. Vol 41/12, Dec. 2001, pp. 2023-2040.
5. W.A. Pleskacz, C.Ouyang and W.Maly. A DRC Based Algorithm for Extraction of Critical Areas for Opens in Large VLSI Circuits. IEEE Trans. on Computer-Aided Design, vol. 18, no 2, Feb. 1999, pp. 151-162.

Viera Stopjakova
Current-Based Test Techniques for Defect Coverage (45 min)

The advanced trends in recent VLSI circuits production lead towards extremely complex systems that include digital and analog parts, memory architectures, and other embedded blocks on a single chip. The mixed-systems realized in deep sub-micron technologies bring also an emergence of testing that becomes of the utmost importance in order to provide the required quality of production. Since the conventional voltage test strategy is not effective in covering hard-detectable physical defects occurring in recent technologies, other test techniques such as current-based strategies might be used to augment the classical approaches. Examples of built-in current monitors for both static supply current (IDDQ) as well as transient supply current (IDDT) measurement are presented. Although current test techniques are very efficient in detecting a wide class of defects these methods suffer from poor versatility and their use in deep sub-micron technologies is limited. Therefore, a new alternative strategy for classification of defective circuits based on analysis of the circuit’s current response using artificial neural networks is described and the experimental results achieved are presented.

Bibliography:
1. V.Stopjakova, H.Manhaeve. Current Conveyor Based BIC Monitor for IDDQ Testing of Complex CMOS Circuits. Proc. of European Design & Test Conference, Paris, France, March 27-30, 1997, pp. 266-270.
2. V.Stopjakova, H.Manhaeve, M.Sidiropulos. On-chip Transient Current Monitor for Testing of Low-Voltage CMOS IC. Proceedings of Design, Automation and Test in Europe - DATE99 Conference, Munich, Germany, March 9-12, 1999, pp. 538-542.
3. D.Micuzik, V.Stopjakova,, L.Benuzkova. Application of Feed-forward Artificial Neural Networks to the Identification of Defective Analog Integrated Circuits, Neural Computing & Applications, Vol. 11, No. 1, June 2002, pp. 71-79.

Raimund Ubar
Hierarchical defect-oriented test generation (45 min)

Complexity problems in test generation and fault simulation for digital systems are handled by raising the abstraction levels from gate to higher system representation levels – to register transfer, instruction set architecture (ISA) or behavioral levels. On the other hand,because of the need of higher accuracy and quality of testing todays submicron integrated circuits, defect orientation is gaining more and more attention. But this increases even more the complexity. As a compromise of the two opposite trends today – defect orientation and high-level modeling - hierarchical approaches are emerging in the test field. The main topics of the lecture are: overview about defect modeling by Boolean differential equations, mapping physical defects onto the logic and higher levels, combining the hierarchical approach with defect orientation, comparing bottom-up and top-down approaches to hierarchical test generation, using Binary and High-Level Decision Diagrams for creating uniform multi-level techniques for automated defect oriented test program generation for complex digital systems.

Bibliography:
1. R.Ubar, J.Raik. Testing Strategies for Networks on Chip. In “Networks on Chip” by A.Jantsch, H.Tenhunen. Kluwer Academic Publishers, 2003, pp. 131-152.
2. T.Cibáková, M.Fischerová, E.Gramatová, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Test Generation for Combinational Circuits with Real Defects Coverage. Pergamon Press. Journal of Microelectronics Reliability, Vol. 42, 2002, pp.1141-1149.
5. W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. Proc. of International Symposium on Quality Electronic Design – ISQED, San Jose, USA, March 2001, pp.365-371.
3. J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. Journal of Electronic Testing: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, 2000.

Ondrej Novak and Zdenek Pliva
Design for Testability and BIST (90 minutes)

The lecture is focused on the problem of IC testability improvement. The diagnostic access standards IEEE 1149.1-6 and the prepared standard IEEE 1500 form a basis on which an IC diagnostic subsystem can be built. In the lecture we describe different Test Access Mechanisms (TAM). We discuss effectiveness of the scan chain diagnostic access methods; Boundary Scan based methods and Random Access Scan methods. One of the important features of the TAM is the power consumption during test. It can be relatively high for shifting test patterns through long chains. We discuss the possibilities of power consumption reduction of the scan chained diagnostic access methods and of the Random Access Scan techniques.
The diagnostic access scan techniques form a platform for Built-In Self Test Equipment design. Based on the diagnostic access standards, different autonomous pattern generators and test response compaction methods can be designed. We explain the published BIST solutions and compare the diagnostic hardware overhead, test data reduction and test time. Several methods of pseudorandom, weighted random and pseudoexhaustive test pattern generation can be used in BIST. Finite automata like Linear Feedback Shift Registers and Cellular Automata are often used as automata that generate and decompress test patterns and that create and store the IC output response signature. The most effective are those that use weighted random test patterns. As the weighed random testing cannot overcome the problem of hard-to-test faults, mixed-mode test approaches are commonly adopted. In these approaches deterministic testing is mixed with pseudo-random or weighted-random testing. We compare these methods and give recommendation how to use them effectively. For designs with dissipated energy and test time restrictions the autonomously generated test patterns are not suitable and deterministic test patterns are used. We discuss the methods of deterministic test pattern compression and decompression and we compare the hardware overhead, amount of stored data and the time for test.

Bibliography:
1. Novak O., Pliva Z., Nosek J., Hlawiczka A., Garbolino T., Gucwa K., : Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor, Kluwer Academic Publishers - Journal of Electronic Testing: Theory and Applications 20, ISSN 0923-8174, pp.109-122, 2004
2. Novák, O., Nosek, J. : Test Pattern Decompression Using a Scan Chain. Proc. of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems , 24-26 October 2001, San Francisco, California. ISBN 0-7695-1203-8, pp. 110-115
3. E. J. Marinissen, Y. Zorian, R. Kapur, T. Taylor, and L. Whetsel.Towards a Standard for Embedded Core Test: An Example. Proc. of the IEEE International Test Conference , pp. 616-627. IEEE, 1999.

Zdenek Kotásek:
Partial Scan Methodologies – a Survey (45 min)

Two principles of applying a test will be mentioned briefly: those based on full scan approach and on utilising transparent properties of an RTL structure. Then, the reasons for reducing the number of FFs included into a scan chain will be explained (test application time, chip area overhead). The classification of partial scan methodologies to testability analysis based, test generation based and structural analysis based methodologies will be demonstrated. The principles of the methodologies will be explained. New approaches based on optimising the process of selecting registers for partial scan will be demonstrated.

Data about the previous presentation of the tutorial:
Presented as one of lectures at the tutorial held in Tallinn, Estonia in October 2002.

Artur Jutman:
Interconnect BIST with Boundary Scan and Beyond (45 min)

The tutorial will embrace the topic of board-level interconnect BIST with the main stress made upon issues related to at-speed testing and the multi-driver contention problem. An introduction into interconnect testing and evolution of related approaches will be presented first. The IEEE Std. 1149.1 (Boundary Scan) will be discussed together with different related test pattern generation methods and their properties. Then the lector will consider the latest developments in at-speed interconnect BIST with and without the aid of the Boundary Scan.

Bibliography:
1. A. Jutman, “Shift Register Based TPG for At-Speed Interconnect BIST”, in Proc. of 24th International Conference on Microelectronics (MIEL’04), Nis, Yugoslavia, May 16-19, 2004.
2. E.J. Marinissen, B. Vermeulen, H. Hollmann, R.G. Bennetts, „Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint,“ in IEEE D&T of Comp., March-April 2003, pp. 8-18.
3. R.Pendurkar,A.Chatterjee,Y.Zorian,”Switching Activity Gen¬¬eration with Automated BIST Synthesis for Performance Tes¬ting of Interconnects,”IEEE Trans CAD/ICS,vol.20,n.9,2001.
4. B.Nadeau-Dostie,et.al,”An Embedded Technique for At-Speed Interconnect Testing,” in Proc. ITC’1999, pp.431-438.
5. A.Attarha,M.Nourani,”Testing Interconnects for Noise and Skew in Gigahertz SoC,” in Proc of ITC’2001, pp.305-314.
6. S.Park,T.Kim,”A new IEEE 1149.1 boundary scan design for the detection of delay defects,” Proc.DATE’2000,pp.458-462.
7. A.J.Hassan,J.Rajski,V.K.Agrawal,”Testing and Diagnosis of Interconnects using Boundary Scan Architecture,” Proc. Int’l Test Conf., 1988, pp.126-137.
8. W.Feng,F.J.Meyer,F.Lombardi,“Novel control pattern gene¬rators for interconnect testing with Boundary Scan,” in Proc. Int’l Symp. Defect and Fault Tolerance in VLSI Systems, 1999, pp. 112-120.