Tutorial I and Tutorial
II are being organized under EU funded IST project
REASON as joint events of the DDECS 2004 Workshop on April
18, 2004:
| Tutorial
I |
Defect-oriented Testing
April 18, 2004, 9:00 – 13:00
Overview of different test
approaches and physical defects is given. Example of
shorts is used to analyze the Boolean behavior of the
defect and to define realistic fault model for this
type of spot defect. The results are extended to other
test strategies (IDDQ, delay) and to other types of
defects (floating gate, gate-oxide short). A methodology
for probabilistic modeling of defects and estimating
the effectiveness of test patterns to detect the defects
is discussed. Current-based strategy is presented, to
augment the conventional voltage test approach. Examples
of built-in current monitors for static supply current
(IDDQ) and transient supply current (IDDT) measurement
are presented. A new strategy based on using artificial
neural networks is described to classify defective circuits.
Hierarchical approach is presented as a compromise of
two opposite trends - defect modeling and high-level
fault manipulation - to cope with complexities of todays
systems.
Keywords: physical
defect behavior, fault models, probabilistic defect
modeling, voltage and current-based testing, hierarchical
test generation
Audience: undergraduate
and PhD students, university teachers, test engineers,
ASIC and system designers, and CAD developers
|
Tutorial II |
Additional Hardware for IC Testability Improvement
April 18, 2004, 14:30 – 18:30
The tutorial will be focused on methods of IC testability
improvement. We will compare different diagnostic access
methods and possibilities of designing a system of BIST.
We will discuss effectiveness and power consumption
of the scan chain diagnostic access methods.
Two principles of applying a test will be mentioned
briefly: those based on full scan approach and on utilising
transparent properties of an RTL structure. The classification
of partial scan methodologies to testability analysis
based, test generation based and structural analysis
based methodologies will be demonstrated.
The last part of the tutorial will embrace the topic
of board-level interconnect BIST with the main stress
made upon issues related to at-speed testing and the
multi-driver contention problem.
Keywords: testability, test generation, full
and partial scan techniques, built-in self-test methods
Audience: undergraduate and PhD students, university
teachers, test engineers, ASIC and system designers,
and CAD developers
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