Final programme
MONDAY
April 19 |
08:30 - 09:00 |
Welcome |
|
09:00 - 10:00 |
Keynote presentation
|
From BIST to BISD |
10:00 - 10:30 |
Coffe break |
|
10:30 - 12:15 |
Session I |
SoC, HW&SW Co-design |
12:15 - 13:00 |
Poster session I |
|
13:00 - 14:30 |
Lunch |
|
14:30 - 15:30 |
Session II |
Bio-inspired HW; Physical Design |
15:30 - 16:00 |
Coffe break |
|
16:00 - 17:15 |
Session III |
Analog/Mixed and RF Test |
18:00 - 19:30 |
Dinner |
|
19:30 - 21:00 |
Student’s session |
|
TUESDAY
April 20 |
08:30 - 09:30 |
Keynote presentation |
System Design Challenges in Ubiquitous Computing Environments |
09:30 - 10:30 |
Session IV |
BIST |
10:30 - 10:45 |
Coffe break |
|
10:45 - 11:30 |
Session V |
Design for Testability and Diagnosis |
| 11:30 - 12:30 |
Panel Session |
|
12:30 |
DDECS 2005 |
Announcement |
12:30 - 14:00 |
Lunch |
New Design Technologies - challenge to Test Engineers
Training |
14:00 - 18:30 |
Social event |
|
19:30 - 24:00 |
Banquet
|
|
WEDNESDAY
April 21 |
08:30 - 09:30 |
Keynote presentation |
Multi-paradigm formal models for circuit validation
and verification |
09:30 - 10:15 |
Session VI |
Design Verification/Validation and Formal Methods |
10:15 - 10:30 |
Coffe break |
|
10:30 - 11:15 |
Poster session II |
|
11:15 - 13:00 |
Session VII |
ASICs/FPGA Design |
13:00 - 14:30 |
Lunch |
|
14:30 - 16:30 |
Session VIII |
Defect/Fault Tolerance |
16:00 |
Workshop closing |
|
MONDAY -
April 19, 2004
| 8:30 - 9:00 |
Welcome |
| 9:00 - 10:00 |
Keynote presentation I
chair: Zebo Peng, Univ. Linkoping, Sweden
From BIST to BISD
Hans-Joachim Wunderlich, University
of Stuttgart, Germany |
| 10:00 - 10:30 |
Coffee break |
| 10:30 - 12:15 |
Session I - SoC, HW&SW
Co-design
chair: Isabel Teixeira, IST/INESC-ID, Lisboa,
Portugal |
| 10:30 - 11:00 |
UML-Driven Design Space Delimitation and Exploratation:
A Case Study on Networks-on-Chip
Leonardo S. Indrusiak, Manfred Glesner, Univ. of Darmstadt,
Germany
Marco Kreutz, Altamiro Susin, Ricardo A.L. Reis, GME Informatica
Porto, Brasil |
| 11:00 - 11:30 |
Performance Evaluation and Implementation of Two Adaptive
Routing Algorithms for XGFT Networks Heikki Kariniemi,
Jari Nurmi, Tampere Univ., Finland |
| 11:30 - 12:00 |
Reconfigurable System on-a-Programmable-Chip Platform
Martin Danek, Petr Honzík, Jirí Kadlec,
Rudolf Matoušek, Zdenek Pohl, Inst. of Information
Theory and Automation and Czech Technical Univ. Prague,
Czech Rep. |
| 12:00 - 12:15 |
Low-Power Design for Microcontroller-based Embedded
Systems
Zdravko Karakehayov, Technical Univ.
of Sofia, Bulgaria |
| 12:15 - 13:00 |
Poster session I
chair: Witold Pleskacz, Warsaw Univ. of Technology,
Poland |
| |
1. Fast Discrete Cosine Transform Algorithms Implemented
in FPGA Structures for Real-Time Image Compression
A. Dabrowska, K. Wiatr, Univ. of Science and Technology,
Krakow, Poland
2. A 120 mW 8-BIT 80 MSPS Oversampled Pipeline Analog-to-Digital
Convertor
S. Halder, A. Chatterjee, A. Banerjee, Indian Inst.
of Technology, India
3. FPGA Implementation of Arithmetic Unit for Modular
Arithmetic
J. Hlavac, R. Lorencz, Czech Technical Univ., Prague,
Czech rep.
4. Balanced Decomposition as a Universal Method for FPGA
Based Digital Designing
M. Rawski, P. Tomaszewicz, T. Luba, Warsaw Univ.
of Technology Poland
5. Scalable Shifter Synthesis for a Finite Field Arithmetic
Unit
J. Schmidt, M. Novotný, Czech Technical Univ.,
Prague, Czech rep.
6. Generating Control Schemes and Entities Recognition
in SystemC Specifications Synthesis from ANSI C code with
OpenMP Directives
P. Dziurzanski, V. Beletskyy, Technical Univ. of
Szczecin, Poland
7 . Iterative ECC Decoder with very Sparse Matrices Solution
K. Vlcek, Jirí Vorac, Jiri Mitrych Technical
Univ. of Ostrava and Phobos, Ltd. Czech.Rep.
8 . Hardware and Software for Stress Test Examination
M. Stork, Univ. of West Bohemia, Plzen, Czech Rep.
9 . A Circuit Clustering Technique Aimed at Reducing the
Total Amount of Intereconnect Resource Used in an FPGA
Colin Doyle, Siobhán Launders, Univ. of Dublin,
Ireland
10. Generic, Compact, and Type-Safe SystemC Models via
Template Metaprogramming
K. Berezowski, Wroclaw Univ. of Technology, Poland |
| 13:00 - 14:30 |
Lunch |
| 14:30 - 15:30 |
Session II - Bio-inspired HW;
Physical Design
chair: Michel Renovell, LIRMM, France |
| 14:30 - 15:00 |
The First Circuits Evolved in a Physical Virtual Reconfigurable
Device
Štepán Friedl, Lukáš
Sekanina, Brno Univ. of Technology, Czech Rep. |
| 15:00 - 15:30 |
Problems and Routing Structure for High -Frequency Microprocessor
Power Distribution
Qing K. Zhu, Alex Waizman,
Intel Corporation Matrix Semiconductor, Inc. USA |
| 15:30 - 16:00 |
Coffee break |
| 16:00 - 17:15 |
Session III - Analog/Mixed,
RF Test
chair: Bernd Straube, FhG IIS/EAS, Dresden,
Germany |
| 16:00 - 16:30 |
Neural Network-Based Detection of Catastrophic Defects
in Analog IC using Wavelet Decomposition
Viera Stopjaková, Pavol Malošek, Marek
Matej, Daniela Duracková, Slovak Univ. of Technology,
Bratislava, Slovakia |
| 16:30 - 17:00 |
Signal Path Sensitization for Built-In-Seft-Test in
Integrated RF Transceivers
Jerzy Dabrovski, Lin Li, Linköping University,
Sweden |
| 17:00 - 17:15 |
Dynamic Prediction for Analogue Circuit Behaviour Using
State-Space Based Transient Faults Analysis
H.J. Kadim, School of Engineering JM Univ. Liverpool,
UK |
| 18:00 - 19:30 |
Dinner |
| 19:30 - 20:30 |
Student session
chair: Richard Ruzicka, Brno Univ. of Technology,
CZ |
| 19:30 - 19:50 |
A General-Purpose Spatial Locality Metric
J. Alakarhu, J. Niittylahti, Tampere Univ. of Technology,
Finland |
| 19:50 - 20:10 |
16-Bit Self-timed Look-Ahead Adder
P. Wang, Univ. of Newcastle upon Tyme, U.K. |
| 20:10 - 20:30 |
Implementation of the RIJNDAEL Algorithm for Data Encryption
M. Baláž, V. Ladecký, R. Ševcík,
Inst. of Informatics, Bratislava, Slovakia |
| 20:30 - 21:00 |
Student poster session
chair: Martin Danek, Inst. of Information
Theory and Automation, Prague, CZ |
| |
1. Graphic Tool for Parallel I-Paths Analysis
D. Mika, Brno Univ. of Technology, Czech rep.
2 . STUMPS Architecture Generation by Java Applet
T. Pikula, R. Ševcík, Inst. of Informatics
and Slovak Univ. of Technology, Bratislava, Slovakia
3 . System for the License Plate Detection and Image Compression
Using Hardware
L. Crha, Brno Univ. of Technology, Czech rep.
4 . A Novel Method for Reducing Clock Skew in Circuits
N. Sarangi, M. Somaiya,Sri Venkateshwara College
of Engg, India
5 . A Neuronmos, Two Inverter, Inverted Literal Circuit
Based on Recharge Logic, for Multiple-Valued Logic Post
Algebraic Applications
J. Lomsdalen, Y. Berg, Dept. of Informatics, Oslo,
Norway |
Tuesday
- April 20, 2004
| 8:30 - 9:30 |
Keynote presentation II
chair: Sybille Hellebrand, Univ. of Insbruck, Austria
System Design Challenges in Ubiquitous Computing Environments
Manfred Glesner, TU Darmstadt, Germany |
| 9:30 - 10:30 |
Session IV. - BIST
chair: Christian Landrault, LIRMM, France |
| 9:30 - 10:00 |
Self-testing of Sequential Circuits Designed for Implementation
in FPGA's with Embedded Memory Blocks
Andrzej
Krasniewski, Warsaw Univ. of Technology, Poland |
| 10:00 - 10:30 |
Built-In Self-Test Preparation in FPGAs
Abilio
Parreira, Joao Teixeira, Marcelino Santos, IST / INESC-ID,
Lisboa, Portugal |
| 10:30 - 10:45 |
Coffee break |
| 10:45 - 11:30 |
Session V. - Design
for Testability and Diagnosis
chair: Joao Paolo Teixeira, IST/INESC-ID,
Lisboa, Portugal |
| 10:45 - 11:15 |
Architecture for Testing and Debugging of System-on-Chip
Components
Ralf Ludewig, Thomas Hollstein, Falko
Schutz, Manfred Glesner, Univ. of Darmstadt ,Germany |
| 11:15 - 11:30 |
Improving Testability Parameters of Pipelined Circuits
Through the Identification of Testable Cores
Zdenek
Kotásek,Tomáš Pecenka, Josef Strnadel,
Brno Univ. of Technology, Czech Rep. |
| 11:30 - 12:30 |
Panel Session
Design & Test Education and Training in Europe - What
are Main Challenges?
chair: Paolo Prinetto, Politecnico di Torino,
Italy |
| 12:30 - 14:00 |
Lunch |
| 14:00 - 18:30 |
Social event |
| 19:30 - 24:00 |
Banquet |
Wednesday
- April 21, 2004
| 8:30 - 9:30 |
Keynote presentation III
chair: Norbert Fristacky, Slovak Univ. of
Technology, Bratislava, Slovakia
Multi-paradigm Formal Models for Circuit Validation
and Verification
Dominique Borrione, TIMA Grenoble,
France |
| 9:30 - 10:15 |
Session VI. - Design
Verification/Validation and Formal Methods
chair: Zdenek Kotasek, Brno Univ. of Technology,
CZ |
| 9:30 - 10:00 |
An Efficient Flip-Flops Matching Engine
Solaiman
Rahim, Jerome Rampon, Bruno Rouzeyre, Lionel Torres, LIRMM
Montpellier, France |
| 10:00 - 10:15 |
UML-Based Visual Design of Embedded Systems
István Majzik, Gergely Pinter, Tamas Kovacs, BUTE
Budapest, Hungary |
| 10:15 - 10:30 |
Coffee break |
| 10:30 - 11:15 |
Poster session II
chair: Viera Stopjakova, Slovak Univ. of
Technology, Bratislava, Slovakia |
| |
1. Enhancing Hierarchical ATPG with a Functional Faulty
Model for Multiplexers
J. Raik, R. Ubar, TU Tallinn,
Estonia
2. Efficient TPG for a Fast At-Speed Interconnect BIST
A. Jutman, TU Tallinn, Estonia
3 . An Efficient Mixed-Mode BIST Technique
P.
Fišer, H. Kubátová, Czech Technical
Univ., Czech Rep.
4. A proposal to Increase Storage Time of Analogue Ram
(ARAM) Cells
Rego Kozma, F. Kovacs, Gyula Horvath., Csaba Horváth.,
BUTE, Budapest, Hungary
5. Trasparent Tests for Intra-Word memory Faults
A. Zankovich, V. Yarmolik, Belarussian State Univ. of
Informatics and Radioelectronics, Belarus
6. Diagnosis of SC-Circuits Using SPICE Simulation in
the Discrete-Time Domains
M. Stanoeva, A. Popov,
Technical Univ. of Sofia, Bulgaria
7. Spice Diagnostic Models of Analog and Analog-Discrete
Electronic Circuits
M. Stanoeva, E. Gadjeva,
L.Raykovska, T. Kouyoumdjiev, Technical Univ. of Sofia,
Bulgaria
8. Design of a Sensory Control System
George
K. Adam, Technological Educational Institute of Larissa,
Greece
9. Two Pattern Generators without ROM for Detection of
Delay Faults
T. Rudnicki, Silesian Univ. of Gliwice, Poland
10. Measurements of Effective Resolution of ADC in Microconvertor
ADUC824
J. Vedral, J. Holub, Czech Technical Univ, Prague,
Czech rep. |
| 11:15 - 13:00 |
Session VII. - ASICs/FPGA
Design
chair: Raimund Ubar, Tallinn Univ. of Technology,
Estonia |
| 11:15 - 11:45 |
An FPGA Implementation of a Montgomery Multiplier over
GF (2^M)
Nele Mentens, Siddika Berna Örs,
Bart Preneel, Joos Vandewalle, Katholieke Univ. of Leuven,
Belgium |
| 11:45 - 12:15 |
Simple PLL-Based True Random Number Generator for Embedded
Digital Systems
Martin Šimka, Miloš
Drutarovský, Technical Univ. of Košice, Slovakia
V. Fischer, Frederic Celle, Univ. Jean Monnet, Saint Etienne,
France |
| 12:15 - 12:45 |
On Connecting Cores to Packet Switched On-Chip Networks:
A Case Study With MicroBlaze Processor Cores
Rickard Holsmark, Alf Johansson, Shashi Kuma, Jönköping
Univ., Sweden |
| 12:45 - 13:00 |
Self-time Multiplier with Data Dependent Computation
Time
Ján Butaš, Daniela Duracková, Chiu-Sing
Choy, Cheong-Fat Chan, Slovak Univ. of Technology Bratislava
and CUHK Honkong |
| 13:00 - 14:30 |
Lunch |
| 14:30 - 16:00 |
Session VIII. - Defect/Fault
Tolerance
chair: Andras Pataricza, Budapest Univ. of
Technology and Economics, Hungary |
| 14:30 - 15:00 |
Robustness Test of CMOS Circuits based on its Wors Case
Power Consumption Analysis Using ATE and GA-MIT Technique
Eric Liau, Doris Schmitt-Landsiedel, Infineon, Technologies
AG, University of Munich, Germany |
| 15:00 - 15:30 |
A Generic Dual Core Architecture
Andreas Steininger,
Thomas Kottke, Robert Bosch GmbH and Univ. of Vienna,
Austria |
| 15:30 - 15:45 |
Dependability Evaluation by Fault Injection into Multithreaded
Application
Anna Derezinska, Warsaw Univ. of Technology,
Poland |
| 15:45 - 16:00 |
A Monitoring Concept for an Automotive Distributed Network
- the Flexray Example
Martin Horauer, Eric Armengaud,
Andreas Steininger, Roman Pallierer, Hannes Friedl, Univ.
of Vienna, Decomsys GmbH, Austria |
| 16:00 |
Workshop closing |
|
