Keynote Speakers and Abstracts

Prof. Dominique Borrione University Joseph Fourier Leader of the research group "Modeling and Verification of Digital Systems" (VDS) TIMA Laboratory Grenoble, France

Multi-paradigm formal models for circuit validation and verification

Abstract: Mark The inclusion of integrated circuits in safety-critical applications requires that the correctness of hardware designs be ensured by rigorous methods. To achieve error-free designs, simulation is still the most commonly used validation technique. Yet the application of formal methods can provide a valuable alternative, by ensuring complete correctness. Many aspects of a chip behavior have to be considered, and no single verification paradigm can apply to all of them. So we consider value simulation as the first method to gain initial confidence in the design, at all levels of abstraction; equivalence checkers at logic level, as well as general purpose theorem proving at more abstract levels for the proof of correctness; symbolic model checking as well as theorem proving for the proof of properties. To include formal verification in the design flow, as a complementary technique to the other usual CAD tools, standard HDL inputs must be accepted.
Formal methods, supported by automatic checkers, are routinely applied at the register transfer level (RTL). But when the specification is more abstract, both the initial validation and the first implementation verification involve extensive simulation and expert human time. Hence, the RTL input to the synthesis software rarely has been proven compliant to the higher-level specification. The introduction of symbolic simulation can help solve this difficulty, by exhibiting synergies between numeric and symbolic techniques. The combination of symbolic simulation with theorem proving for the functional aspects, or with model checking for the control part of a design, will be presented and illustrated.

Abstract: Mark Weiser imagined the forthcoming ubiquitous computing systems as specialized elements of hardware and software, connected by means of both wired and wireless technologies. Eventually, such elements should gracefully melt into the environment and become so ubiquitous that no one will notice their presence.
In such a world composed of advanced communication components, highly sophisticated sensors, smart pens and tabs, the design of those "ubiquitous" gadgets has to comply with a multitude of characteristics like proactivity, transparency, ease-of-use, high-level performance and energy management, cyber foraging and surrogate request support, location and context awareness, scalability, and so forth.
Such scenarios can be imagined due to technology shrinking: the maximum die size enlarges, and integrating complete systems of continuously increasing complexity becomes possible. However, technology improvements bring with them several challenges and drawbacks. In order to cope with those problems, a multitude of design paradigms like reconfigurable architectures, platform based design, IP reuse, orthogonalization of concerns, communication abstraction, and power aware design emerged during the last decade.
This talk tries to give an insight in the challenges imposed on system design of ubiquitous systems and to discuss emerging hardware architectures and design methodologies with a special focus on reconfigurable architectures, embedded systems, SoC integration and power consumption.

From BIST to BISD

Abstract: Embedded test and self-test are considered as major means to overcome the challenges of testing highly complex nanometer systems. They may reduce the requirements for the external test equipment, for test bandwidth, and for test application time at the cost of diagnostic resolution.
But short time to market and short time to volume require fast and efficient ways for debug and diagnosis. Deeply embedded cores and an increasing amount of diagnostic data to be transported to and from these cores prohibit just switching off the BIST-structures.
The talk will point out current trends to reuse BIST-structures for diagnosis and will discuss appropriate modification of these structures. A collection of integrated sensors, monitors and dedicated logic structures will lead to the new paradigm of built-in self-diagnosis. This approach may form the basis for ensuring improvements of reliability and availability of nanometer structures by applying an extended use of self-repair, self-reconfiguration and self-healing concepts.